In order to save space on printed circuit boards the level of integration of electronic components should be raised further and further. To this end some components are now beginning to be stacked vertically and connected three-dimensionally to form so-called 3D-ICs. The vertical connection of individual components is preferably realized in TSV technology (Through-Silicone-Via). Using TSV technology the connection between individual horizontal layers is effected by vertical metallic connections with a diameter of up to approx. 5 μm. These 3D-TSV-ICs are characterized by a high level of integration relative to their footprint and behave extremely robustly.
As such a 3D-integrated circuit (3D-IC) is a circuit which consists of a vertical stack of thinned individual chips. Seen from outside the circuit looks like a monolithic circuit, but strictly speaking is more like a hybrid circuit, but with a higher level of integration than typical hybrid circuits. The aim of 3D-integration is to achieve a still higher functionality of the ICs for a same-size footprint of the housing. Individual chip planes in the 3D-ICs are connected using through-contacting with the aid of TSVs. TSV, at the moment, represents the best available technology for realizing the high demands for the electric paths (short, robust, etc.).
The increased rejection rate which is due to the high level of integration can be minimized in that testing is carried out not only on the finished ICs and the individual components, but also on the stack whenever a new component is added to the existing stack and through-contacted.
US 2006/0290369 A1 discloses an electronic device testing unit for testing IC chips by means of pressing their input/output connections against contact units of a test head. The electronic device testing unit is provided in the form of a test plate with test plate body. The test plate comprises holders for holding the rear surfaces of IC chips, which surfaces do not comprise any protruding input/output connections, but which surfaces are essentially smooth holding surfaces. During the time of testing the holders are held on the test plate body in a swingable manner. The side surfaces of the holders are guided by means of guide surfaces, which are provided in the vicinity of the contact units. The IC chips are held by means of the holders.
US 2011/0018564 A1 discloses a wafer prober, which is provided with a storage space, one or more alignment units, contact units and a storage transport section. The storage space supports a wafer at a certain position, transports it to a further processing position of the wafer and is located at the further processing position. One or more alignment units position the wafer at a certain position relative to the storage space. The contact units are arranged in a number which is greater than that of the alignment units and they carry out an examination further processing in contact with the wafer at the further processing position. A storage space section transports the wafer between the alignment unit and the contact unit. The storage space is provided with three or more pin holes, an alignment marking and an alignment section.
This results in that many defects can be recognized at a very early stage of manufacture and can possibly even be repaired. Should one of the required components found to be defective, there is then no need to remove the finished module, but the defective component can be replaced before assembly by a component which has been tested and found to be OK.
Normally the ICs are held on the substrate until they are finished and it is only then that they are singularized by sawing the substrate. Intermediate tests prior to completion of the individual ICs are therefore normally carried out on the substrate.
There is however also the possibility via TSV to connect a processor module with e.g. a separately manufactured storage module. Therefore, one of the components may already have been singularized before it is tested. Testing of already singularized components is carried out in carriers, on which a larger number of components may have been fixed in their exact positions. In the following therefore the word “carrier” is used, independently of whether the components are components on a substrate or already singularized components on a carrier. Similarly, wafer or parts thereof are to be regarded as components not yet separated.
With components of this kind on a carrier, for example a processor on a substrate, which is to be connected via TSVs with a further component configured as a storage, contacts are provided on the substrate opposite to the component, and on that side which is to be connected with the further component. A reliable test can only be carried out if both kinds of contact can be contacted simultaneously.
In order to make an accurate association between the contacts of the electronic component and the test contacts, it has previously been sufficient to center the components mechanically. In view of the small distance, however, in particular of the contacts on the side of the electronic component, at which side a further component is to be connected, this is no longer sufficient. Mechanical centering comprises tolerances which are partly larger than the distances between individual contacts. Therefore errors during testing are unavoidable.